Three dimensional interconnection method and electronic device obtained by same

ABSTRACT

A method of interconnection in three dimensions and to an electronic device obtained by the method. To increase the compactness of integrated circuit modules, the method stacks and adhesively bonds packages containing a chip connected to output leads by connection conductors inside each package, cuts through the packages near the chips to form a block, the conductors being flush with the faces of the block, and makes the connections on the faces of the block by metalizing and then etching the outlines of the connections. The method also applies to the matching of packages in the replacement of obsolete circuits.

The invention relates to a method of interconnection in three dimensionsfor packages containing at least one electronic component. It alsorelates to an electronic device obtained by this method.

The production of current electronic systems, whether civil or military,must take into account the requirements of ever increasing compactness,because of the ever increasing number of circuits involved.

In this search for greater compactness, it has already been proposed toproduce stacks of integrated circuit chips or, as described in Frenchpatent FR 2 688 630, chip-encapsulating packages, the interconnectionbeing accomplished in three dimensions using the faces of the stack asinterconnection surfaces for making the necessary connections betweenoutput leads.

The encapsulation of chips in plastic packages, such as for example thestandard packages of SOJ (Small Outline J-lead), TSOP (Thin SmallOutline Package) or CSP (Chip Scale Package) type has many advantages.Firstly, these packages have been tested and burned-in by themanufacturer, although these operations are very difficult to carry outon bare chips. Moreover, it is generally difficult to obtain bare chipsfrom manufacturers. The combination of these reasons therefore makes itpreferential to use packages, which are appreciably less expensive andeasier.

The stacking of packages according to the solution of the abovementionedpatent involves the following main operations: straightening the outputleads in order to facilitate alignment and molding; stacking of theplastic packages; encapsulation with resin and curing; cutting of theblock; metalization; etching of the outlines of the connections on thefaces of the block. Moreover, since the cutting is carried out on theoutside of the packages in order to use the output leads of the packagesfor the interconnection in three dimensions, the 3D module obtainedalways has, in the plane of the packages, dimensions greater than theoriginal packages.

The object of the invention is, on the one hand, to simplify theoperations of manufacturing a 3D module and, on the other hand, toappreciably reduce the volume occupied. It is based on the idea ofcutting the block not any longer on the outside of the packages, butthrough these packages.

According to the most general aspect of the invention, what is thereforeprovided is a method of interconnection in three dimensions for at leastone package containing at least one electronic component and furnishedwith connection conductors for connecting, inside said package,connection pads on the component to output leads toward the outside ofthe package, said method being characterized in that it comprises thefollowing steps:

a) stacking and assembling the elements to be interconnected;

b) cutting through the package or packages, near said components, inorder to form a block leaving the cross section of the connectionconductors flush;

c) production of the electrical connections between the conductors ofthe various elements on the faces of said block.

More particularly, for interconnecting several packages together,provision is made for said stacking and assembling step a) to consist instacking and adhesively bonding the packages.

This method thus dispenses with the operations of straightening theoutput leads and of encapsulation and curing, the latter being replacedby a simple adhesive bonding operation. The method has thus beensimplified.

Moreover, the cutting of the block is carried out near the chips, andtherefore through the packages, and no longer on the outside of thepackages, hence a reduction of almost 50% in the area of the block in aplane parallel to the packages.

To achieve this solution to the problems of reducing the volume of theelectronic devices, it is clear that it was necessary, on the one hand,to go counter to the idea that a package is needed for variousfunctions, namely protection against the external environment, handlingnot hazardous to the chip and electrical connection to the outside, andmust not be cut, and that it was necessary, on the other hand, to statethat the transfer molding resins used on the inside of the packages bythe semiconductor industry were substantially of the same compositionand filler content as the encapsulation resins used in the prior art.

Another, particularly beneficial, application relates to the replacementof complex components rendered obsolete, that is to say no longeravailable on the market, when, for example, a new series of an old pieceof equipment has to be manufactured. During the original design of theequipment, ASIC circuits were able in particular to be defined, whichwere produced by a supplier who, since then, has changed technology.Hitherto, it was necessary to redevelop a new ASIC. However, there areprogrammable integrated circuits with a sea of ports, of the FPGA (FieldProgrammable Gate Array) which would make it possible to program thesame functions as the original ASIC circuit. The drawback is that thearrangement, the number of outputs and the dimensions of the ASICcircuit are different from those of the FPGA circuits available: ingeneral, the FPGA circuits, with very large-scale integration, have asubstantially larger number of outputs than the ASIC circuit that itwould be desired to replace. To produce the functions of an ASIC with 44outputs for example, only this number of outputs of an FPGA circuit (forexample with 144 outputs) would be used. In addition, the arrangement ofthese outputs will not be the same, hence a mismatch with respect to thecard on which this circuit has to be mounted. Finally, there is a riskof the footprint of the FPGA circuit being different and, in general,larger.

The invention makes it possible, through its principle, to solve theseproblems. According to this new application, provision is made toassociate with a complex circuit contained in a package a matchingcircuit consisting of a printed circuit, of a first array of selectionconductors, allowing it to be connected to the suitable outputs of thepackage, and of a second, matching array, the leads of which reproduce,in terms of number and arrangement, the desired pattern, the printedcircuit providing the interconnection between the two arrays.

By implementing the invention, it is thus possible to produce anelectronic circuit with interconnection in three dimensions, of smallfootprint, suitable for the desired application.

This other aspect of the invention therefore provides a method, asgenerally defined above, for interconnecting a package with a circuitfor matching the array of the output leads, characterized in that saidstacking and assembly step a) consists in stacking and assembling saidmatching circuit against said package by adhesive bonding orencapsulation.

The invention will be more clearly understood and further features andadvantages will become apparent from the description below and from theappended drawings in which:

FIG. 1 is a view of the inside and from above of a package showing theconnections of a chip to the output leads;

FIG. 2 is a sectional view of the package of FIG. 1 in the plane B;

FIG. 3 shows the block diagram of the method according to the invention;

FIG. 4 is a sectional view of how the packages are assembled during onestep of the method according to the invention;

FIG. 5 is a partial perspective view of the 3D module obtained;

FIG. 6 illustrates an initial step of an application variant of theinvention;

FIGS. 7 and 8 show sectional views during successful steps of thevariant of FIG. 6;

FIG. 9 is a side view of the module obtained; and

FIG. 10 is the block diagram of the method according to this variant ofthe invention.

FIG. 1 shows, by way of example and in a simplified manner, the insideof a TSOP package seen from above. A chip 1 (for example a memory chip)has connection pads 10 aligned in two rows. These pads are connected toan array 4 of output leads 40 via a set 3 of connecting conductors 30.The link between the pads 10 and the conductors 30 is made by connectingup the wires 11. The assembly is enclosed in a plastic package 2.

FIG. 2 shows the package 2 in section in the plane B. The conductors 30terminate in bent-over output leads 40.

The method according to the invention, applied to the mutualinterconnection in three dimensions of packages, is illustrated by theblock diagram of FIG. 3. In a first step 100, the packages are stackedand assembled by adhesive bonding as shown in FIG. 4, in which thereference 5 denotes films of adhesive between the packages.

In a second step 101, the assembly is cut, not at the output leads inthe plane A for example (FIG. 1), as in the prior art, but through thepackages 2, in the plane of cutting A′ (or B′) near the chip 1 so as tocut the connection conductors 30, the section 31 of which is flush withthe faces of the block obtained.

As may be seen, the planes of sections such as A′ or B′ are much closerto the chip 1, hence a considerably reduced footprint. For example, thesawing may be carried out at a distance of between 0.5 and 2 mm aroundthe chip, depending on the chip wire-bonding techniques used by thesemiconductor manufacturer.

Step 102 then consists in making the connections between the conductorsof the various packages to the faces of the block obtained. Varioustechniques can be used to do this. Preferably, in a first stage 1021,the faces of the block are metalized and, in a second stage 1022, theoutline of the connections are etched, for example by laser etching. Theblock 6 obtained is shown in FIG. 5. It may be seen that the section 31of the connection conductors of the packages 2 are connected byconnections 71 on the faces of the block 6, which may terminate inconnection pads 72 toward the outside or to the sections 77 of theoutput arrays 78 of the block. This step of the process is described indetail in, for example, the aforementioned patent FR 2 688 630.

As may be seen, the method according to the invention allows themanufacture of the 3D modules to be simplified by eliminating theoperation of straightening the output leads or tabs, since they areremoved during the cutting, and by replacing the encapsulation andcuring step with a single adhesive bonding operation.

Another application of the invention will now be described within thecontext of the replacement of a specific circuit of the ASIC type with acircuit of general application of the FPGA type, which may be programmedin order to fulfil the functions of the original ASIC circuit. Asalready explained, such a programming operation means in general thatonly some of the ports and outputs of the FPGA circuit are used and thearrangement of the outputs has to be redistributed in order to bematched to the application envisioned.

To do this, knowing the number of outputs to be used and theirdistribution, a matching circuit CA (FIG. 6) is produced, whichcomprises a first selection array 52 placed on one face and on the edgesof a printed circuit 50 facing the package 20 of the FPGA circuit. Thispackage contains at least one chip 12 whose connection pads (not shown)are connected to the leads 42 of an output array via conductors 41. Theleads 52 of the selection array are positioned so as to correspond tothe conductors 41 used, in what will be the plane of cutting C.Moreover, the opposite face of the printed circuit 50 carries, along itsedges, a matching array of output leads 53, the positioning of which isthat of the leads of the ASIC circuit that it is wished to replace. Theinterconnection between the two arrays is effected by means of thetracks of the printed circuit 50. The leads 52 are soldered to thesetracks by the soldered joints 54 and the leads 53 by the soldered joints55. For assembling the package and the matching circuit CA, an arraysupport 60 is provided, the end 56 of the leads of the array 53 engagingin the slots of the array support.

In a first step 100′ (FIG. 10), the package 20 and the matching circuitCA are assembled so that the plane of cutting C is near the chip 12 andcuts off the ends of the arrays 52 and 53. The assembling operation isperformed, for example, using beads of adhesive placed on both faces ofthe printed circuit 50. The total amount of adhesive must be sufficientto fill the volumes lying between the printed circuit 50 and the package20 and the array support 60, respectively, and so that an excess flowsout at 70 during assembling, so as to allow the sawing through the coreof the adhesive (with neither an empty space nor holes). Under thepressure used to assembly the package 20 to the support 60, as has justbeen mentioned, the adhesive flows out in order to coat the ends of theleads 52 and 53, as shown at 70 in FIG. 7. The assembling operation mayalso be performed by encapsulation between package and support 60 with acurable resin, such as an epoxy resin.

The next step 101′ consists, as previously, in cutting through thepackage through the plane C.

A block M is thus obtained, seen in partial section in FIG. 8, in whichthe conductors 41 and the leads of the arrays 52 and 53 are flush withthe face of the block. This FIG. 8 furthermore shows that the end 56 ofthe leads of the matching array have been suitably bent over.

Step 102′ (FIG. 10) then consists in making, on the faces of the blockM, the desired connections in three dimensions between the conductors 41of the package and the leads of the first selection array 52, using anyconventional technology.

For example, the faces of the block are metalized (1021′) and then theoutlines of the connections are etched (1022′) for example by laseretching.

FIG. 9 shows, seen from the side, the module M obtained. On the faceshown may be seen the sections of the conductors 41, of the selectionarray 52 and of the matching array 53. The metalization 80 covers allthe faces of the block M. Laser etching 81 is used to etch the outlineof the connections between conductors 41 and leads of the array 52 andto isolate the leads of the matching array 53. For example, a usedoutput 410 of the package is connected via the connection 73 to the lead520. In contrast, outputs such as 411 are not used.

Of course, the illustrative examples described in no way limit theinvention; in particular, techniques other than complete metalization ofthe block could be used to make the connections in 3D, or etchingmethods other than laser etching could be used. Provision could also bemade not to extend the leads 53 beyond the edge of the printed circuit,which would avoid having to make them flush and therefore having toisolate them by etching. However, since the interconnection between theoutput array 56 and the electronic circuit 12 is achieved by solderingthe array to the printed circuit 50, for applications requiring highreliability in a harsh environment, it is undesirable for there to be arisk of the solder (tin/lead, whose melting point is in general 180° C.)reflowing when the assembly is itself soldered to a printed circuit cardhaving all the other components. The interconnection via the metalizedface of the block therefore makes this connection of the array 56secure. However, for many noncritical applications, the fact of simplysoldering the array to the printed circuit 50 constitutes a realsimplification.

What is claimed is:
 1. A method of interconnection in three dimensions for at least two packages each containing at least one electronic component and furnished with connection conductors for connecting, inside the at least two packages, connection pads on each of at least one electronic component to output leads toward an outside of the at least two packages, the method comprising: a) stacking and assembling the at least two packages to be interconnected; b) cutting through the at least two packages, near the electronic components, to form a block leaving cross sections of the connection conductors flush on faces of the block; c) producing electrical connections between the cross sections of the connection conductors that are flush on the faces of the block.
 2. The method as claimed in claim 1, for interconnecting plural packages together, wherein said stacking and assembling a) includes stacking and adhesively bonding the plural packages.
 3. The method as claimed in claim 1, wherein each electronic component is an electronic chip, and the cutting b) is carried out at a distance of between about 0.5 and 2 mm from the electronic chips.
 4. The method as claimed in claim 1, wherein the producing the electrical connections c) comprises: c1) metalizing the faces of the block; and c2) etching outlines of the connections.
 5. The method as claimed in claim 4, wherein etching the outlines of the connections c2) is carried out by laser etching.
 6. A method of interconnection in three dimensions for at least one package that contains at least one electronic component and is furnished with connection conductors inside the at least one package, and a matching circuit including a printed circuit, of a first selection array and of a second matching array, said first and second arrays being placed along edges of the matching circuit, the method comprising: a) stacking and assembling the matching circuit against the at least one package; b) cutting through the at least one package, near the electronic components, to form a block leaving cross section of the connection conductors flush on faces of the block; c) making electrical connections between the cross sections of the connection conductors that are flush on the faces of the block.
 7. The method as claimed in claim 6, for interconnecting the at least one package with a circuit for matching an array of output leads, wherein the stacking and assembly a) includes stacking and assembling the matching circuit against the at least one package by adhesive bonding or encapsulation.
 8. The method as claimed in claim 7, wherein said matching circuit includes a printed circuit along edges of which, on a face that faces the at least one package, a first array for selecting the output leads of the package to be connected and a second matching array are placed, the matching circuit is assembled with the at least one package so that a plane of cutting cuts off ends of the first and second arrays of the matching circuit.
 9. The method as claimed in claim 6, wherein the at least one electronic component is an electronic chip, and the cutting b) is carried out at a distance of between 0.5 and 2 mm from the electronic chips.
 10. An electronic device with interconnection in three dimensions, comprising packages that contain at least one electronic component and are furnished with connection conductors inside the packages, in which electronic device, the packages are stacked and adhesively bonded, wherein the electronic device is formed by a block cut through the packages near the electronic components so that the connection conductors are flush with faces of the block, and wherein the faces of the block bear connections connecting the connection conductors.
 11. An electronic device with interconnection in three dimensions, comprising: a package that contains at least one electronic component and is furnished with connection conductors inside the package; a matching circuit with which the package is assembled and including a printed circuit of a first selection array and of a second matching array, the first and second arrays being placed along edges of the printed circuit, on first and second faces of the printed circuit, respectively, the first face carrying the first array facing the package and the package/matching circuit assembly having been cut through the package, and ends of the first and second arrays form a block in which a section of the connection conductors and of the first and second arrays is flush with faces of the block, and wherein the faces of the block carry connections connecting said connection conductors to the first selection array.
 12. The electronic device as claimed in claim 11, wherein the faces of the block are metalized and etched to define outlines of said connections and to isolate the sections of the second array. 